The present invention relates to communication apparatus and in particular, but not exclusively, to a PCI Express interconnect apparatus.
In many computer environments, a fast and flexible interconnect system can be desirable to provide connectivity to devices capable of high levels of data throughput. In the fields of data transfer between devices in a computing environment, PCI Express (PCI-E) can be used to provide connectivity between a host and one or more client devices or endpoints. PCI Express is becoming a de-facto I/O interconnect for servers and desktop computers. PCI Express allows physical system decoupling (CPU <-> I/O) through high-speed serial I/O. The PCI Express Base Specification 1.0 sets out behavior requirements of devices using the PCI Express interconnect standard. According to the Specification, PCI Express is a host to endpoint protocol where each endpoint connects to a host and is accessible by the host. PCI Express imposes a stringent tree structure relationship between I/O Devices and a Root Complex.
An interconnect apparatus, for example a switch, will need to process and transmit large volumes of transaction packets. These transaction packets can be of different types that are buffered separately. Buffers are typically implemented using hardware in which the area available (“real estate”) on, for example, an integrated circuit such as an application specific integrated circuit (ASIC) is at a premium. It is therefore desirable to implement a buffer in a manner which requires a minimum of real estate.